{
  "headers": ["Generation", "Announced", "Core Design", "What Changed", "Status Today"],
  "rows": [
    ["Power5", "2004", "POWER5, up to 64 processors (595)", "Introduced Micro-Partitioning and simultaneous multithreading; eServer i5/p5 lines", "Out of standard IBM support since staged 2019-2020 withdrawals"],
    ["Power6", "2007", "POWER6, up to 5.0 GHz", "System i and System p unified into Power Systems (April 2008); major clock-speed jump", "Out of standard IBM support since March 31, 2019"],
    ["Power7", "2010", "POWER7, up to 8 cores per chip", "On-chip eDRAM cache, further PowerVM virtualization advances", "Out of, or near, standard IBM support depending on model"],
    ["Power8", "2014", "POWER8, up to 12 cores per chip", "CAPI acceleration, NVLink on some models, PCIe Gen3", "Approaching or past standard IBM support depending on model"],
    ["Power9", "2017", "POWER9, up to 24 cores per chip", "PCIe Gen4, OpenCAPI, designed for the AI/GPU acceleration era", "Within standard IBM support, entering its later support years"],
    ["Power10", "2021", "POWER10, up to 15 cores per chip (dual-chip module)", "PCIe Gen5, built-in AI matrix-math acceleration engines", "Currently within IBM's standard support window"],
    ["Power11", "2025", "POWER11, current-generation core design", "IBM's current flagship Power Systems generation", "Current generation, full support lifecycle ahead"]
  ]
}